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? semiconductor components industries, llc, 2016 august, 2016 ? rev. 1 1 publication order number: ncd5701/d ncd5701a, ncd5701b, NCD5701C high current igbt gate drivers the ncd5701a, ncd5701b and NCD5701C are high?current, high?performance stand?alone igbt drivers for high power applications that include solar inverters, motor control and uninterruptible power supplies. the devices offer a cost?effective solution by eliminating external output buffer. devices protection features include accurate under?voltage?lockout (uvlo), desaturation pro tection (desat) and active low fault output. the drivers also feature an accurate 5.0 v output. the drivers are designed to accommodate a wide voltage range of bias supplies including unipolar and ncd5701b even bipolar voltages. depending on the pin configuration the devices also include active miller clamp (ncd5701a) and separate high and low (v oh and v ol ) driver outputs for system design convenience (NCD5701C). all three available pin configuration variants have 8?pin soic package. features ? high current output (+4/?6 a) at igbt miller plateau voltages ? low output impedance for enhanced igbt driving ? short propagation delay with accurate matching ? direct interface to digital isolator/opto?coupler/pulse transformer for isolated drive, logic compatibility for non?isolated drive ? desat protection with programmable delay ? tight uvlo thresholds for bias flexibility ? wide bias voltage range ? this device is pb?free, halogen?free and rohs compliant ncd5701a features ? active miller clamp to prevent spurious gate t urn?on ncd5701b features ? negative output voltage for enhanced igbt driving NCD5701C features ? separate outputs for v ol and v oh typical applications ? solar inverters ? motor control ? uninterruptible power supplies (ups) marking diagram www. onsemi.com soic?8 d suffix case 751 see detailed ordering and shipping information on page 9 o f this data sheet. ordering information pin connections 1 8 ncd5701 = specific device code x = a, b or c a = assembly location l = wafer lot y = year w = work week = pb?free package ncd5701x alyw 1 8 ncd5701a clamp gnd vo vcc vin vref flt desat ncd5701b vee gnd vo vcc vin vref flt desat NCD5701C gnd vol voh vcc vin vref flt desat 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 2 figure 1. simplified application schematics vcc desat vcc gnd clamp vo vref vin flt ncd5701a vcc vee desat vcc vee gnd vref vin flt vo ncd5701b vcc desat vcc gnd voh vol vref vin flt NCD5701C
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 3 figure 2(a). detailed block diagram ncd5701a v ref q q set clr s r q q set clr s r q q set clr s r v uvlo v mc-thr v desat-thr clamp desat v in v ref v cc v cc bandgap gnd + - + - + - i desat-chg tsd delay delay flt r in-h v o ? ? vref flt clamp desat vin gnd vo vcc vref vcc vcc desat tsd uvlo clamp ncd5701a figure 2(b). simplified block diagram ncd5701a
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 4 v ref q q set clr s r q q set clr s r v uvlo v desat-thr desat v in v ref v cc v cc bandgap gnd + - + - i desat-chg tsd delay delay flt r in-h v o ? figure 3(a). detailed block diagram ncd5701b figure 3(b). simplified block diagram ncd5701b logic unit ldo vref flt vee desat vin gnd vo vcc vref vcc vcc desat tsd uvlo ncd5701b
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 5 v ref q q set clr s r q q set clr s r v uvlo v desat-thr v ol desat v in v ref v cc v cc bandgap gnd + - + - i desat-chg tsd delay delay v oh flt r in-h ? figure 4(a). detailed block diagram NCD5701C figure 4(b). simplified block diagram NCD5701C logic unit ldo vref flt gnd desat vin vol voh vcc vref vcc vcc desat tsd uvlo NCD5701C
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 6 table 1. pin function description pin name no. i/o/x description vin 1 i input signal to control the output. in applications which require galvanic isolation, vin is generat- ed at the opto output, the pulse transformer secondary or the digital isolator output. there is a signal inversion from vin to vo (voh/vol). vin is internally clamped to 5.5 v and has a pull? up resistor of 1 m to ensure that an output is low in the absence of an input signal. a minimum pulse?width is required at vin before vo (voh/vol) is activated. vref 2 o 5 v reference generated within the driver is brought out to this pin for external bypassing and for powering low bias circuits (such as digital isolators). flt 3 o fault output (active low) that allows communication to the main controller that the driver has encountered a fault condition and has deactivated the output. capable of driving optos or digital isolators when isolation is required. (truth table is provided in the datasheet to indicate condi- tions under which this signal is asserted.) desat 4 i input for detecting the desaturation of igbt due to a fault condition. a capacitor connected to this pin allows a programmable blanking delay every on cycle before desat fault is processed, thus preventing false triggering. vcc 5 x positive bias supply for the driver. the operating range for this pin is from uvlo to the maxi- mum. a good quality bypassing capacitor is required from this pin to gnd and should be placed close to the pins for best results. vo (ncd5701a, ncd5701b) 6 o driver output that provides the appropriate drive voltage, source and sink current to the igbt gate. vo is actively pulled low during start?up and under fault conditions. voh (NCD5701C) 6 o driver high output that provides the appropriate drive voltage and source current to the igbt gate. vol (NCD5701C) 7 o driver low output that provides the appropriate drive voltage and sink current to the igbt gate. vol is actively pulled low during start?up and under fault conditions. gnd (ncd5701a, ncd5701b) 7 x this pin should connect to the igbt emitter with a short trace. all power pin bypass capacitors should be referenced to this pin and kept at a short distance from the pin. gnd (NCD5701C) 8 x this pin should connect to the igbt emitter with a short trace. all power pin bypass capacitors should be referenced to this pin and kept at a short distance from the pin. vee (ncd5701b) 8 x a negative voltage with respect to gnd can be applied to this pin and that will allow vo to go to a negative voltage during off state. a good quality bypassing capacitor is needed from vee to gnd. if a negative voltage is not applied or available, this pin must be connected to gnd. clamp (ncd5701a) 8 i/o provides clamping for the igbt gate during the off period to protect it from parasitic turn?on. to be tied directly to igbt gate with minimum trace length for best results.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 7 table 2. absolute maximum ratings (note 1) rating symbol minimum maximum unit differential power supply v cc ?v ee (v max ) 0 36 v positive power supply v cc ?gnd ?0.3 22 v negative power supply v ee ?gnd ?18 0.3 v gate output high (v o , v oh )?gnd v cc + 0.3 v gate output low (v o , v ol )?gnd v ee ? 0.3 v input voltage v in ?gnd ?0.3 5.5 v desat voltage v desat ?gnd ?0.3 v cc + 0.3 v flt current sink source i flt ?sink i flt ?src 20 25 ma power dissipation so?8 package pd 700 mw maximum junction temperature t j(max) 150 c storage temperature range tstg ?65 to 150 c esd capability, human body model (note 2) esdhbm 4 kv esd capability, machine model (note 2) esdmm 200 v moisture sensitivity level msl 1 ? lead temperature soldering reflow (smd styles only), pb?free versions (note 3) t sld 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (eia/jesd22?a114) esd machine model tested per aec?q100?003 (eia/jesd22?a115) latchup current maximum rating: 100 ma per jedec standard: jesd78, 25 c 3. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d. table 3. thermal characteristics rating symbol value unit thermal characteristics, soic?8 (note 4) thermal resistance, junction?to?air (note 5) r ja 176 c/w 4. refer to electrical characteristics and application information for safe operating area. 5. values based on copper area of 100 mm 2 (or 0.16 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. table 4. operating ranges (note 6) rating symbol min max unit differential power supply v cc ?v ee (v max ) 30 v positive power supply v cc uvlo 20 v negative power supply v ee ?15 0 v input voltage v in 0 5 v input pulse width t on 40 ns ambient temperature t a ?40 125 c 6. refer to electrical characteristics and application information for safe operating area. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 8 table 5. electrical characteristics v cc = 15 v, v ee = 0 v, kelvin gnd connected to v ee . for typical values t a = 25 c, for min/max values, t a is the operating ambient temperature range that applies, unless otherwise noted. parameter test conditions symbol min typ max unit logic input and output input threshold voltages high?state (logic 1) required low?state (logic 0) required no state change pulse?width = 150 ns, v en = 5 v voltage applied to get output to go low voltage applied to get output to go high voltage applied without change in output state v in?h1 v in?l1 v in?nc 4.3 1.2 0.75 3.8 v input internal pull?up resistance to vref r in?h 1 m input current high?state low?state v in?h = 4.5 v v in?l = 0.5 v i in?h i in?l 1 10 a input pulse?width no response at the output guaranteed response at the output voltage thresholds consistent with input specs t on?min1 t on?min2 30 10 ns flt threshold voltage low state high state (i flt ?sink = 15 ma) (i flt ?src = 20 ma) v flt ?l v flt ?h 12 0.5 13.9 1.0 v drive output output low state i sink = 200 ma, t a = 25 c i sink = 200 ma, t a = ?40 c to 125 c i sink = 1.0 a, t a = 25 c v ol1 v ol2 v ol3 0.1 0.2 0.8 0.2 0.5 1.2 v output high state i src = 200 ma, t a = 25 c i src = 200 ma, t a = ?40 c to 125 c i src = 1.0 a, t a = 25 c v oh1 v oh2 v oh3 14.5 14.2 13.8 14.8 14.7 14.1 v peak driver current, sink (note 7) r g = 0.1 , v cc = 15 v, v ee = ?8 v v o = 13 v v o = 9 v (near miller plateau) i pk?snk1 i pk?snk2 6.8 6.1 a peak driver current, source (note 7) r g = 0.1 , v cc = 15 v, v ee = ?8 v v o = ?5 v v o = 9 v (near miller plateau) i pk?src1 i pk?src2 7.8 4.0 a dynamic characteristics turn?on delay (see timing diagram) negative input pulse width = 10 s t pd?on 45 56 75 ns turn?off delay (see timing diagram) positive input pulse width = 10 s t pd?off 45 63 75 ns propagation delay distortion (=t pd?on ? t pd?off ) for input or output pulse width > 150 ns, t a = 25 c t a = ?40 c to 125 c t distort1 t distort2 ?15 ?25 ?7 5 25 ns prop delay distortion between parts (note 7) t distort ?tot ?30 0 30 ns rise time (see timing diagram) c load = 10 nf t rise 18 ns fall time (see timing diagram) c load = 10 nf t fall 19 ns delay from flt under uvlo/ tsd to vo/vol t d1?out 10 12 15 s delay from desat to vo/vol (note 7) t d2?out 220 ns 7. values based on design and/or characterization.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 9 table 5. electrical characteristics v cc = 15 v, v ee = 0 v, kelvin gnd connected to v ee . for typical values t a = 25 c, for min/max values, t a is the operating ambient temperature range that applies, unless otherwise noted. parameter unit max typ min symbol test conditions dynamic characteristics delay from uvlo/tsd to flt (note 7) t d3?flt 7.3 s miller clamp (ncd5701a only) clamp voltage i sink = 500 ma, t a = 25 c i sink = 500 ma, t a = ?40 c to 125 c v clamp 1.0 0.7 1.2 1.4 2.2 v clamp activation threshold v mc?thr 1.8 2.0 2.2 v desat protection desat threshold voltage v desat?thr 6.0 6.35 7.0 v blanking charge current i desat?chg 0.22 0.25 0.28 ma blanking discharge current i desat?dis 30 ma uvlo uvlo startup voltage v uvlo?out?on 13.2 13.5 13.8 v uvlo disable voltage v uvlo?out?off 12.2 12.5 12.8 v uvlo hysteresis v uvlo?hyst 1.0 v vref voltage reference i ref = 10 ma v ref 4.85 5.00 5.15 v reference output current for <100 mv dropout i ref 10 ma recommended capacitance c vref 100 nf supply current current drawn from v cc v cc = 15 v standby (no load on output, flt , vref) i cc?sb 0.9 1.5 ma current drawn from v ee (ncd5701b only) v ee = ?10 v standby (no load on output, flt , vref) i ee?sb ?0.2 ?0.14 ma thermal shutdown thermal shutdown temperature (note 7) t sd 188 c thermal shutdown hysteresis (note 7) t sh 33 c 7. values based on design and/or characterization. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. ordering information device package shipping ? ncd5701adr2g soic?8 (pb?free) 2500 / tape & reel ncd5701bdr2g soic?8 (pb?free) 2500 / tape & reel NCD5701Cdr2g soic?8 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 10 typical characteristics figure 5. propagation delay vs. temperature temperature ( c) 100 80 60 40 20 0 ?20 ?40 40 50 60 70 80 figure 6. fault to output low delay figure 7. output rise/fall time temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 10 11 12 13 14 15 100 80 60 40 20 0 ?20 ?40 10 15 20 25 figure 8. output source current vs. output voltage figure 9. output sink current vs. output voltage v o (v, v cc = 15 v, v ee = ?8 v) v o (v, v cc = 15 v, v ee = ?8 v) 15 10 5 0 ?5 0 1 2 3 4 6 7 8 1 5 10 5 0 ?5 0 1 2 3 4 5 7 8 propagation delay (ns) fault to output delay ( s) rise/fall time (ns) i o (a) i o (a) 120 t pd?on t pd?off 120 120 t rise t fall 6 5
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 11 typical characteristics figure 10. v ref voltage vs. current figure 11. v ref voltage vs. temperature i ref (ma) temperature ( c) 10 8 6 4 2 0 4.95 4.96 4.98 4.99 5.00 100 80 60 40 20 0 ?20 ?40 4.95 4.97 5.00 5.02 5.05 figure 12. desat charge current vs. temperature figure 13. desat threshold voltage vs. temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 240 250 260 100 80 60 40 20 0 ?20 ?40 6.2 6.3 6.4 6.5 figure 14. uvlo threshold voltages figure 15. v o vs. v in at 25 c (v cc = 15 v, v ee = 0 v) v cc , supply voltage (v) v in (v) 15 14 13 12 11 10 0 5 10 15 5 4 3 2 1 0 ?5 0 5 10 15 20 v ref (v) v ref (v) i deset?chg ( a) v desat (v) v o , output voltage (v) v o (v) 4.97 5.01 5.02 5.03 5.04 5.05 120 120 120 uvlo?out?off uvlo?out?on 4.96 4.98 4.99 5.01 5.03 5.04 v ref @ i ref = 0 ma v ref @ i ref = 10 ma
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 12 typical characteristics figure 16. fault output, sourcing 20 ma figure 17. fault output, sinking 15 ma temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 13 14 15 100 80 60 40 20 0 ?20 ?40 0 0.5 1.0 v flt?h (v) v flt?l (v) 120 120 figure 18. v clamp at 0.5 a (ncd5701a only) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0.5 1.0 1.5 2.0 2.5 v clamp (v) 120 figure 19. supply current vs. switching frequency (v cc = 15 v, v ee = ?10 v, 25 c) frequency (khz) 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 supply current (ma) i cc i ee (ncd5701b only)
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 13 applications and operating information this section lists the details about key features and operating guidelines for the ncd5701. high drive current capability the ncd5701 driver family is equipped with many features which facilitate a superior performance igbt driving circuit. foremost amongst these features is the high drive current capability. the drive current of an igbt driver is a function of the differential voltage on the output pin (v cc ?voh/vo for source current, vol/vo?v ee for sink current) as shown in figure 20. figure 20 also indicates that for a given voh/vol value, the drive current can be increased by using higher v cc /v ee power supply). the drive current tends to drop off as the output voltage goes up (for turn?on event) or goes down (for turn?off event). as explained in many igbt application notes, the most critical phase of igbt switching event is the miller plateau region where the gate voltage remains constant at a voltage (typically in 9?11 v range depending on igbt design and the collector current), but the gate drive current is used to charge/discharge the miller capacitance (c gc ). by providing a high drive current in this region, a gate driver can significantly reduce the duration of the phase and help reducing the switching losses. the ncd5701 addresses this requirement by providing and specifying a high drive current in the miller plateau region. most other gate driver ics merely specify peak current at the start of switching ? which may be a high number, but not very relevant to the application requirement. it must be remembered that other considerations such as emi, diode reverse recovery performance, etc., may lead to a system level decision to trade off the faster switching speed against low emi and reverse recovery. however, the use of ncd5701 does not preclude this trade?off as the user can always tune the drive current by employing external series gate resistor. important thing to remember is that by providing a high internal drive current capability, the ncd5701 facilitates a wide range of gate resistors. another value of the high current at the miller plateau is that the initial switching transition phase is shorter and more controlled. finally, the high gate driver current (which is facilitated by low impedance internal fets), ensures that even at high switching frequencies, the power dissipation from the drive circuit is primarily in the external series resistor and more easily manageable. experimental results have shown that the high current drive results in reduced turn?on energy (e on ) for the igbt switching. figure 20. output current vs. output voltage drop when driving larger igbts for higher current applications, the drive current r equirement is higher, hence lower r g is used. larger igbts typically have high input capacitance. on the other hand, if the ncd5701 is used to drive smaller igbt (lower input capacitance), the drive current requirement is lower and a higher r g is used. thus, for most typical applications, the driver load rc time constant remains fairly constant. caution must be exercised when using the ncd5701 with a very low load rc time constant. such a load may trigger internal protection circuitry within the driver and disable the device. figure 21 shows the recommended minimum gate resistance as a function of igbt gate capacitance and gate drive trace inductance. figure 21. recommended minimum gate resistance as a function of igbt gate capacitance
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 14 gate voltage range the negative drive voltage for gate (with respect to gnd, or emitter of the igbt) is a robust way to ensure that the gate voltage does not rise above the threshold voltage due to the miller ef fect. in systems where the negative power supply is available, the vee option offered by ncd5701b allows not only a robust operation, but also a higher drive current for turn?off transition. adequate bypassing between vee pin and gnd pin is essential if this option is used. the v cc range for the ncd5701 is quite wide and allows the user the flexibility to optimize the performance or use available power supplies for convenience. under voltage lock out (uvlo) this feature ensures reliable switching of the igbt connected to the driver output. at the start of the driver?s operation when v cc is applied to the driver, the output remains turned?off. this is regardless of the signals on v in until the v cc reaches the uvlo output enabled (v uvlo?out?on ) level. after the v cc rises above the v uvlo?out?on level, the driver is in normal operation. the state of the output is controlled by signal at v in . if the v cc falls below the uvlo output disabled (v uvlo?out?off ) level during the normal operation of the driver, the fault output is activated and the output is shut?down (after a delay) and remains in this state. the driver output does not start to react to the input signal on v in until the v cc rises above the v uvlo?out?on again. the waveform showing the uvlo behavior of the driver is in figure 22. in an igbt drive circuit, the drive voltage level is important for drive circuit optimization. if v uvlo?out?off is too low, it will lead to igbt being driven with insuf ficient gate voltage. a quick review of igbt characteristics can reveal that driving igbt with low voltage (in 10?12 v range) can lead to a significant increase in conduction loss. so, it is prudent to guarantee v uvlo?out?off at a reasonable level (above 12 v), so that the igbt is not forced to operate at a non?optimum gate voltage. on the other hand, having a very high drive voltage ends up increasing switching losses without much corresponding reduction in conduction loss. so, the v uvlo?out?on value should not be too high (generally, well below 15 v). these conditions lead to a tight band for uvlo enable and disable voltages, while guaranteeing a minimum hysteresis between the two values to prevent hiccup mode operation. the ncd5701 meets these tight requirements and ensures smooth igbt operation. it ensures that a 15 v supply with 8% tolerance will work without degrading igbt performance, and guarantees that a fault will be reported and the igbt will be turned off when the supply voltage drops below 12.2 v. a uvlo event (v cc voltage going below v uvlo?out?off ) also triggers activation of flt output after a delay of t d3?flt . this indicates to the controller that the driver has encountered an issue and corrective action needs to be taken. however, a nominal delay t d1?out = 12 s is introduced between the initiation of the flt output and actual turning off of the output. this delay provides adequate time for the controller to ini tiate a more orderly/sequenced shutdown. in case the controller fails to do so, the driver output shutdown ensures igbt protection after t d1?out . figure 22. uvlo function and limits timing delays and impact on system performance the gate driver is ideally required to transmit the input signal pulse to its output without any delay or distortion. in the context of a high?power system where igbts are typically used, relatively low switching frequency (in tens of khz) means that the delay through the driver itself may not be as significant, but the matching of the delay between different drivers in the same system as well as between different edges has significant importance. with reference to figure 23(a), two input waveforms are shown. they are typical complementary inputs for high?side (hs) and low?side (ls) of a half?bridge switching configuration. the dead?time between the two inputs ensures safe transition between the two switches. however, once these inputs are through the driver, there is potential for the actual gate voltages for hs and ls to be quite different from the intended input waveforms as shown in figure 23(a). the end result could be a loss of the intended dead?time and/or pulse?width distortion. the pulse?width distortion can create an imbalance that needs to be corrected, while the loss of dead?time can eventually lead to cross?conduction of the switches and additional power losses or damage to the system. the ncd5701 driver is designed to address these timing challenges by providing a very low pulse?width distortion and excellent delay matching. as an example, the delay matching is guaranteed to t distort2 = 25 ns while many of competing driver solutions can be >250 ns.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 15 figure 23(a). timing waveforms (other drivers) figure 23(b). ncd5701 timing waveforms active miller clamp protection this feature (offered by ncd5701a) is a cost savvy alternative to a negative gate voltage. the main requirement is to hold the gate of the turned?off (for example low?side) igbt below the threshold voltage during the turn?on of the opposite?side (in this example high?side) igbt in the half bridge. the turn?on of the high?side igbt causes high dv/dt transition on the collector of the turned?off low?side igbt. this high dv/dt then induces current (miller current) through the c gc capacitance (miller capacitance) to the gate capacitance of the low?side igbt as shown in figure 24. if the path from gate to gnd has critical impedance (caused by r g ) the miller current could rise the gate voltage above the threshold level. as a consequence the low?side igbt could be turned on for a few tens or hundreds of nanoseconds. this causes higher switching losses. one way to avoid this situation is to use negative gate voltage, but this requires second dc source for the negative gate voltage. an alternative way is to provide an additional path from gate to gnd with very low impedance. this is exactly what active miller clamp protection does. additional trace from the gate of the igbt to the clamp pin of the gate driver is introduced. after the v o output has gone below the active miler clamp threshold v mc?thr the clamp pin is shorted to gnd and thus prevents the voltage on the gate of the igbt to rise above the threshold voltage as shown in figure 25. the clamp pin is disconnected from gnd as soon as the signal to turn on the igbt arrives to the gate driver input. the fact that the clamp pin is engaged only after the gate voltage drops below the v mc?thr threshold ensures that the function of this pin does not interfere with the normal turn?off switching performance that is user controllable by choice of r g .
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 16 figure 24. current path without miller clamp protection figure 25. current path with miller clamp protection desaturation protection (desat) this feature monitors the collector?emitter voltage of the igbt in the turned?on state. when the igbt is fully turned on, it operates in a saturation region. its collector?emitter voltage (called saturation voltage) is usually low, well below 3 v for most modern igbt s. it could indicate an overcurrent or similar stress event on the igbt if the collector?emitter voltage rises above the saturation voltage, after the igbt is fully turned on. therefore the desat protection circuit compares the collector?emitter voltage with a voltage level v desat?thr to check if the igbt didn?t leave the saturation region. it will activate flt output and shut down driver output (thus turn?off the igbt), if the saturation voltage rises above the v desat?thr . this protection works on every turn?on phase of the igbt switching period. at the beginning of turning?on of the igbt, the collector?emitter voltage is much higher than the saturation voltage level which is present after the igbt is fully turned on. it takes almost 1 s between the start of the igbt turn?on and the moment when the collector?emitter voltage falls to the saturation level. therefore the comparison is delayed by a configurable time period (blanking time) to prevent false triggering of desat protection before the igbt collector?emitter voltage falls below the saturation level. blanking time is set by the value of the capacitor c blank . the exact principle of operation of desat protection is described with reference to figure 26. at the turned?off output state of the driver, the desat pin is shorted to ground via the discharging transistor (q dis ). therefore, the inverting input holds the comparator output at low level. at the turned?on output state of the driver, the current i desat?chg from current source starts to flow to the blanking capacitor c blank , connected to desat pin. appropriate value of this capacitor has to be selected to ensure that the desat pin voltage does not rise above the threshold level v desat?thr before the igbt fully turns on. the blanking time is given by following expression. according to this expression, a 47 pf c blank will provide a blanking time of (47p *6.5/0.25m =) 1.22 s. t blank c blank v desat?thr i desat?chg after the igbt is fully turned?on, the i desat?chg flows through the desat pin to the series resistor r s?desat and through the high voltage diode and then through the collector and igbt to the emitter. care must be taken to select the resistor r s?desat value so that the sum of the saturation voltage, drop on the hv diode and drop on the r s?desat caused by current i desat?chg flowing from desat source current is smaller than the desa t threshold voltage. following expression can be used: v desat?thr r s?desat i desat?chg v f_hv diode v cesat_igbt important part for desat protection to work properly is the high voltage diode . it must be rated for at least same voltage as the low side igbt. the safety margin is application dependent . the typical waveforms for igbt overcurrent condition are outlined in figure 27.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 17 figure 26. desaturation protection schematic figure 27. desaturation protection waveforms
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 18 input signal the input signal controls the gate driver output. figure 28 shows the typical connection diagrams for isolated applications where the input is coming through an opto?coupler or a pulse transformer. figure 28. opto?coupler or pulse transformer at input the relationship between gate driver input signal from a pulse transformer (figure 29) or opto?coupler (figure 30) and the output is defined by many time and voltage values. the time values include output turn?on and turn?of f delays (t pd?on and t pd?off ), output rise and fall times (t rise and t fall ) and minimum input pulse?width (t on?min ). note that the delay times are defined from 50% of input transition to first 10% of the output transition to eliminate the load dependency. the input voltage parameters include input high (v in?h1 ) and low (v in?l1 ) thresholds as well as the input range for which no output change is initiated (v in?nc ). 90% 10% t pd-off t pd-on t rise t fall 50% 50% v in-h1 t on-min v in v out v in-nc v in-l1 figure 29. input and output signal parameters for pulse transformer
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 19 v in-h1 v in-l1 v in v out v in-nc t pd-off t pd-on t rise t fall t on-min 90% 10% figure 30. input and output signal parameters for opto?coupler use of vref pin the ncd5701 provides an additional 5.0 v output (vref) that can serve multiple functions. this output is capable of sourcing up to 10 ma current for functions such as opto?coupler interface or external comparator interface. the vref pin should be bypassed with at least a 100 nf capacitor (higher the better) irrespective of whether it is being utilized for external functionality or not. vref is highly stable over temperature and line/load variations ( see characteristics curves for details ) fault output pin this pin provides the feedback to the controller about the driver operation. the situations in which the flt signal becomes active (low value) are summarized in the table 6. table 6. flt logic truth table vin uvlo desat internal tsd vout flt notes l inactive l l h h normal operation ? output high h inactive l l l h normal operation ? output low x active x l l l uvlo activated ? flt low (t d3 - flt ), output low (t d3 - flt + t d1?out ) l inactive h l l l desat activated (only when v in is low) ? output low (t d2_out ), flt low x inactive x h l l internal thermal shutdown ? flt low (t d3 - flt ), out- put low (t d3 - flt + t d1?out ) thermal shutdown the ncd5701 also of fers thermal shutdown function that is primarily meant to self?protect the driver in the event that the internal temperature gets excessive. once the temperature crosses the t sd threshold, the flt output is activated after a delay of t d3 - flt . after a delay of t d1?out (12 s), the output is pulled low and many of the internal circuits are turned off. the 12 s delay is meant to allow the controller to perform an orderly shutdown sequence as appropriate. once the temperature goes below the second threshold, the part becomes active again.
ncd5701a, ncd5701b, NCD5701C www. onsemi.com 20 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncd5701/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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